Trace processors: moving to fourth-generation microarchitectures

Trace Processors: Moving to Fourth-Generation Microarchitectures

F undamentally new generations of microarchi-tectures have been occurring approximately every two decades since the 1940s. Each generation has been driven by advances in underlying hardware technologies, and by attempts to extract and realize higher degrees of instruction-level parallelism. Given this pattern and the continued push for higher performance, we are midway through the third generat...

High-performance Frontends for Trace Processors

Instruction Pre-Processing in Trace Processors

In trace processors, a sequential program is partitioned at run time into “traces.” A trace is an encapsulation of a dynamic sequence of instructions. A processor that uses traces as the unit of sequencing and execution achieves high instruction fetch rates and can support very wide-issue execution engines. We propose a new class of hardware optimizations that transform the instructions within ...

Decoupled Value Prediction on Trace Processors

Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on the predicted outcome. In this paper, we address several implementation issues for value prediction which are important on wide-issue superscalar architectures, and present a value prediction scheme based on the trace ...

Fourth generation bound states

We investigate the spectrum and wave functions of q0q0 bound states for heavy fourth generation quarks (q0) that have a very small mixing with the three observed generations of standard model quarks. Such bound states come with different color, spin and flavor quantum numbers. Since the fourth generation Yukawa coupling, q0 , is large we include all perturbative corrections to the potential bet...